Hi,
es gibt da nen hinweis in der TVIA faq
ZitatAlles anzeigen
Q: There seems to be timing problems with a Pentium 200MHz with CEPC under the following conditions:
PCI bus ,two memory mapped I/O contiguous writes and the two ports are
not in one dword(32 bit ) range or page?
A: This is because the PCI generates a memory write burst to the device,
but the device is doing an I/O cycle, not memory cycle so that causes some timing problems.
To solve it, simply insert a dummy I/O read cycle right after any I/O write , e.g.
Mem_IO_Write 3C6
Mem_IO_Read 3CC (Any port)
Mem_IO_Write 3C9
hab aber nicht weiter geschaut ob es damit was zu tun hat.
CU
9000h